Recently, a resistive random access memory (ReRAM) of storing resistance value information, that is, a high resistance state and a low resistance state, of an electrically-rewritable variable resistive element in a non-volatile manner has attracted attention as a non-volatile memory device. In a well-known structure of such an ReRAM, for example, a plurality of memory cell arrays formed by arranging variable resistance memory cells where variable resistive elements as memory elements and rectifying elements such as diodes are connected in series in an array shape at intersections of a plurality of word lines extending parallel to a first direction and a plurality of bit lines extending parallel to a second direction perpendicular to the first direction are stacked, and the word lines or the bit lines are shared by the memory cell arrays adjacent to each other in the stack direction.
Such a non-volatile memory device is manufactured as follows. A first wiring material layer which is to be a word line and a first memory cell layer including a variable resistive layer which is to be a variable resistive element and a diode layer which is to be a rectifying element are stacked on an interlayer insulating film. Next, the first wiring material layer and the first memory cell layer are etched through a lithography technique and a reactive ion etching technique (hereinafter, referred to as an RIE method) to form a line-and-space pattern extending in the first direction, and the interlayer insulating film is embedded between the patterns. Accordingly, the first wiring material layer becomes the word line. Next, a second wiring material layer which is to be a bit line and a second memory cell layer including a variable resistive layer and a diode layer are stacked on the interlayer insulating film. Next, the second memory cell layer, the second wiring material layer, the first memory cell layer, and the interlayer insulating film are etched through the lithography technique and the RIE method to form a line-and-space pattern extending in the second direction, and the interlayer insulating film is embedded between the patterns. Accordingly, the second wiring material layer becomes the bit line, so that a first-layer memory cell array where memory cells having a columnar structure are arrayed in a matrix shape at the cross-points of the word lines and the bit lines is formed. Next, the same process is repeated, so that a multi-layer memory cell array is formed.
In the related art, when memory cell components of the two layers are processed at one time, in a portion which is in contact with the interlayer insulating film embedded between the memory cell layers of the lower layer side, the interlayer insulating film becomes an eave-shaped portion, so that residues of the memory cell components easily remain. Therefore, in the case where such residues are not removed, there is a problem in that short-circuit occurs in the lower-layer memory cell array due to the residues of the memory cell components in the lower portion between the adjacent memory cells.